1. Field
Example embodiments relate to a processor and a memory controlling method, and more particularly, to a processor and a memory controlling method that may improve a data processing rate.
2. Description of the Related Art
An on-chip memory is used for effectively utilizing a memory in a computer system. The on-chip memory being located between a processor core and an external memory (main memory) operates quicker than the external memory, and has a smaller size than that of the external memory. A cache memory and a Scratch-Pad Memory (SPM) are mainly used as the on-chip memory.
The cache memory is an on-chip memory to which a unique address space is not assigned, and in hardware ascertains whether data exists through a tag check circuitry. Accordingly, since a user may not control storing, changing, and deleting of data, a cache miss may frequently occur. Also, since an additional tag check circuitry may be needed to ascertain whether the data exists, a size of the memory and energy consumption increases.
In the case of the SPM to which a unique address space is assigned, the user or a program may directly ascertain whether the data is stored, and control the data. Therefore, the cache miss may not occur, and the size of the memory and the energy consumption may relatively reduce compared with the cache memory since the additional tag check circuitry is not needed. Therefore, a number of processors containing the SPM increases based on the described reasons.
When a rate of reading data is lower than an operation rate of a processor, a data processing ability of the processor substantially decreases. Also, when a processor core manages both reading data to be processed and processing the read data, the data processing ability of the processor more substantially decreases.
Therefore, to improve the data processing ability of the processor, the data to be processed by the processor core is required to be effectively prepared for the on-chip memory (specifically, SPM) included in the processor.